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? 2007 microchip technology inc. ds20090c-page 1 MCP23016 features ? 16-bit remote bidirectional i/o port - 16 i/o pins default to 16 inputs ?fast i 2 c? bus clock frequency (0 - 400 kbits/s) ? three hardware address pins allow use of up to eight devices ? high-current drive capability per i/o: 25 ma ? open-drain interrupt output on input change ? interrupt port capture register ? internal power-on reset (por) ? polarity inversion register to configure the polarity of the input port data ? compatible with most microcontrollers ? available temperature range: - industrial (i): -40c to +85c cmos technology ? operating supply voltage: 2.0v to 5.5v ? low standby current packages ? 28-pin pdip, 300 mil; 28-pin soic, 300 mil ? 28-pin ssop, 209 mil; 28-pin qfn, 6x6 mm package types block diagram vss gp1.0 gp1.1 gp1.2 gp1.3 int gp1.4 v ss clk tp gp1.5 gp1.6 gp1.7 scl gp0.7 gp0.6 gp0.5 gp0.4 gp0.3 gp0.2 gp0.1 gp0.0 v dd v ss a2 a1 a0 sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdip, soic, ssop qfn 2 3 4 5 6 1 7 gp1.2 gp1.3 int gp1.4 v ss clk tp 15 16 17 18 19 20 21 gp0.3 gp0.2 gp0.1 gp0.0 v dd v ss a2 gp1.5 gp1.6 gp1.7 scl sda a0 a1 23 24 25 26 27 28 22 gp1.1 gp1.0 vss gp0.7 gp0.6 gp0.5 gp0.4 10 11 8 9 121314 MCP23016 MCP23016 16 bits gp0.0 to gp0.7 gp1.0 to gp1.7 write pulse read pulse low pass filter interrupt logic i 2 c? bus control address decoder power-on reset i/o port deserializer serializer/ control clock gen i 2 c? bus interface/ protocol handler int a0 a1 a2 scl sda clkin v dd v ss configuration registers control 8-bit tp iares 16-bit i 2 c ? i/o expander
MCP23016 ds20090c-page 2 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds20090c-page 3 MCP23016 1.0 device overview the MCP23016 device provides 16-bit, general purpose, parallel i/o expansion for i 2 c bus applications. this device includes high-current drive capability, low supply current and individual i/o configuration. i/o expanders provide a simple solution when additional i/os are needed for acpi, power switches, sensors, push buttons, leds and so on. the MCP23016 consists of multiple 8-bit configuration registers for input, output and polarity selection. the system master can enable the i/os as either inputs or outputs by writing the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the read register can be inverted with the polarity inversion register (see section 1.7.3, ?input polarity registers? ). all registers can be read by the system master. the open-drain interrupt output is activated when any input state differs from its corresponding input port register state. this is used to indicate to the system master that an input state has changed. the interrupt capture register captures port value at this time. the power-on reset sets the registers to their default val- ues and initializes the device state machine. three device inputs (a0 - a2) determine the i 2 c address and allow up to eight i/o expander devices to share the same i 2 c bus. 1.1 pin descriptions table 1-1: pinout description pin name pdip, soic, ssop pin no. qfn pin no. i/o/p type buffer type description clk 9 6 i st clock source input tp 10 7 o ? test pin (this pin must be left floating) gp1.0 2 27 i/o ttl d0 digital input/output for gp1 gp1.1 3 28 i/o ttl d1 digital input/output for gp1 gp1.2 4 1 i/o ttl d2 digital input/output for gp1 gp1.3 5 2 i/o ttl d3 digital input/output for gp1 gp1.4 7 4 i/o ttl d4 digital input/output for gp1 gp1.5 11 8 i/o st d5 digital input/output for gp1 gp1.6 12 9 i/o st d6 digital input/output for gp1 gp1.7 13 10 i/o st d7 digital input/output for gp1 gp0.0 21 18 i/o ttl d0 digital input/output for gp0 gp0.1 22 19 i/o ttl d1 digital input/output for gp0 gp0.2 23 20 i/o ttl d2 digital input/output for gp0 gp0.3 24 21 i/o ttl d3 digital input/output for gp0 gp0.4 25 22 i/o ttl d4 digital input/output for gp0 gp0.5 26 23 i/o ttl d5 digital input/output for gp0 gp0.6 27 24 i/o ttl d6 digital input/output for gp0 gp0.7 28 25 i/o ttl d7 digital input/output for gp0 scl 14 11 i st serial clock input sda 15 12 i/o st serial data i/o int 6 3 o od interrupt output a0 16 13 i st address input 1 a1 17 14 i st address input 2 a2 18 15 i st address input 3 v ss 1, 8, 19 5, 16, 26 p ? ground reference for logic and i/o pins v dd 20 17 p ? positive supply for logic and i/o pins
MCP23016 ds20090c-page 4 ? 2007 microchip technology inc. 1.2 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level to deactivate the por circuit (i.e., release reset). a maximum rise time for v dd is specified in the electrical specifications. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature) must be met to ensure proper operation. 1.3 power-up timer (pwrt) the power-up timer provides a 72 ms nominal time- out on power-up, keeping the device in reset and allowing v dd to rise to an acceptable level. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see table 2-4 for details (t pwrt , parameter 3). 1.4 clock generator the MCP23016 uses an external rc circuit to determine the internal clock speed. the user must connect r and c to the MCP23016, as shown in figure 1-1. figure 1-1: clock configuration a 1 mhz (typ.) internal clock is needed for the device to function properly. the internal clock can be measured on the tp pin. recommended r ext and c ext values are shown in table 1-2. 1.5 i 2 c bus interface/ protocol handler this block manages the functionality of the i 2 c bus interface and protocol handling. the MCP23016 supports the following commands: table 1-3: command byte to register relationship 1.6 address decoder the last three lsb of the 7-bit address are user-defined (see table 1-4). three hardware pins () define these bits. table 1-4: device address internal clock MCP23016 v dd r ext c ext v ss clk note: set iares = 1 to measure the clock output on tp. table 1-2: recommended values r ext c ext 3.9 k 33 pf command byte result 0h access to gp0 1h access to gp1 2h access to olat0 3h access to olat1 4h access to ipol0 5h access to ipol1 6h access to iodir0 7h access to iodir1 8h access to intcap0 (read-only) 9h access to intcap1 (read-only) ah access to iocon0 bh access to iocon1 0100a2a1a0
? 2007 microchip technology inc. ds20090c-page 5 MCP23016 1.7 register block the register block contains the configuration and port registers, as shown in table 1-5. table 1-5: register summary name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por port registers gp0 gp0.7 gp0.6 gp0.5 gp0.4 gp0.3 gp0.2 gp0.1 gp0.0 0000 0000 gp1 gp1.7 gp1.6 gp1.5 gp1.4 gp1.3 gp1.2 gp1.1 gp0.0 0000 0000 olat0 ol0.7 ol0.6 ol0.5 ol0.4 ol0.3 ol0.2 ol0.1 ol0.0 0000 0000 olat1 ol1.7 ol1.6 ol1.5 ol1.4 ol1.3 ol1.2 ol1.1 ol1.0 0000 0000 configuration registers ipol0 igp0.7 igp0.6 igp0.5 igp0. 4 igp0.3 igp0.2 igp0.1 igp0.0 0000 0000 ipol1 igp1.7 igp1.6 igp1.5 igp1. 4 igp1.3 igp1.2 igp1.1 igp1.0 0000 0000 iodir0 iod0.7 iod0.6 iod0.5 iod0.4 iod0.3 iod0.2 iod0.1 iod0.0 1111 1111 iodir1 iod1.7 iod1.6 iod1.5 iod1.4 iod1.3 iod1.2 iod1.1 iod1.0 1111 1111 intcap0 icp0.7 icp0.6 icp0.5 icp0 .4 icp0.3 icp0.2 icp0.1 icp0.0 xxxx xxxx intcap1 icp1.7 icp1.6 icp1.5 icp1 .4 icp1.3 icp1.2 icp1.1 icp1.0 xxxx xxxx iocon0 ? ? ? ? ? ? ? iares ---- ---0 iocon1 ? ? ? ? ? ? ? iares ---- ---0 legend: ? 1? bit is set, ?0? bit is cleared, x = unknown, ? = unimplemented.
MCP23016 ds20090c-page 6 ? 2007 microchip technology inc. 1.7.1 data port registers two registers provide access to the two gpio ports: ? gp0 (provides access to data port gp0) ? gp1 (provides access to data port gp1) a read from this register provides status on pins of these ports. a write to these registers will modify the output latch registers (olat0, olat1) and data output. register 1-1: gp0 - general purpose i/o port register 0 register 1-2: gp1 - general purpose i/o port register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp0.7gp0.6gp0.5gp0.4gp0.3gp0.2gp0.1gp0.0 bit 7 bit 0 bit 7-0 gp0.0:gp0.7 : reflects the logic level on the pins. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gp1.7gp1.6gp1.5gp1.4gp1.3gp1.2gp1.1gp1.0 bit 7 bit 0 bit 7-0 gp1.0:gp1.7 : reflects the logic level on the pins. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2007 microchip technology inc. ds20090c-page 7 MCP23016 1.7.2 output latch registers two registers provide access to the two port output latches: ? olat0 (provides access to the output latch for port gp0) ? olat1 (provides access to the output latch for port gp1) a read from these registers results in a read of the latch that controls the output and not the actual port. a write to these registers updates the output latch that controls the output. register 1-3: olat0 - output latch register 0 register 1-4: olat1 - output latch register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol0.7 ol0.6 ol0.5 ol0.4 ol0.3 ol0.2 ol0.1 ol0.0 bit 7 bit 0 bit 7-0 ol0.0:o0.7 : reflects the logic level on the output latch. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ol1.7 ol1.6 ol1.5 ol1.4 ol1.3 ol1.2 ol1.1 ol1.0 bit 7 bit 0 bit 7-0 ol1.0:o1.7 : reflects the logic level on the output latch. 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
MCP23016 ds20090c-page 8 ? 2007 microchip technology inc. 1.7.3 input polarity registers these registers allow the user to configure the polarity of the input port data (gp0 and gp1). if a bit in this reg- ister is set, the corresponding input port (gpn) data bit polarity will be inverted. ? ipol0 (controls the polarity of gp0) ? ipol1 (controls the polarity of gp1) register 1-5: ipol0 - input polarity port register 0 register 1-6: ipol1 - input polarity port register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 igp0.7 igp0.6 igp0.5 igp0.4 igp0.3 igp0.2 igp0.1 igp0.0 bit 7 bit 0 bit 7-0 igp0.0:igp0.7 : controls the polarity inversion for the input pins 1 = corresponding gp0 bit is inverted 0 = corresponding gp0 bit is not inverted legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 igp1.7 igp1.6 igp1.6 igp1.4 igp1.3 igp1.2 igp1.1 igp1.0 bit 7 bit 0 bit 7-0 igp1.0:igp1.7 : controls the polarity inversion for the input pins 1 = corresponding gp1 bit is inverted 0 = corresponding gp1 bit is not inverted legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2007 microchip technology inc. ds20090c-page 9 MCP23016 1.7.4 i/o direction registers two registers control the direction of data i/o: ? iodir0 (controls gp0) ? iodir1 (controls gp1) when a bit in these registers is set, the corresponding pin becomes an input. otherwise, it becomes an output. at power-on reset, the device ports are configured as inputs. register 1-7: iodir0 - i/o direction register 0 register 1-8: iodir1 - i/o direction register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 iod0.7 iod0.6 iod0.5 iod0.4 iod0.3 iod0.2 iod0.1 iod0.0 bit 7 bit 0 bit 7-0 iod0.0:io0.7: controls the direction of data i/o 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 iod1.7 iod1.6 iod1.5 iod1.4 iod1.3 iod1.2 iod1.1 iod1.0 bit 7 bit 0 bit 7-0 iod1.0:io1.7: controls the direction of data i/o 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
MCP23016 ds20090c-page 10 ? 2007 microchip technology inc. 1.7.5 interrupt capture registers two registers contain the value of the port that generated the interrupt: ? intcap0 contains the value of gp0 at time of gp0 change interrupt ? intcap1 contains the value of gp1 at time of gp1 change interrupt these registers are ?read-only? registers (a write to these registers is ignored). register 1-9: intcap0 - interrupt captured value for port register 0 register 1-10: intcap1 - interrupt captured value for port register 1 r-x r-x r-x r-x r-x r-x r-x r-x icp0.7 icp0.6 icp0.5 icp0.4 icp0.3 icp0.2 icp0.1 icp0.0 bit 7 bit 0 bit 7-0 icp0.0:icp0.7: reflects the logic level on the gp0 pins at the time of interrupt due to pin change 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r-x r-x r-x r-x r-x r-x r-x r-x icp1.7 icp1.6 icp1.5 icp1.4 icp1.3 icp1.2 icp1.1 icp1.0 bit 7 bit 0 bit 7-0 icp1.0:icp1.7: reflects the logic level on the gp1 pins at the time of interrupt due to pin change 1 = logic ? 1 ? 0 = logic ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown
? 2007 microchip technology inc. ds20090c-page 11 MCP23016 1.7.6 i/o expander control register ? iocon0 controls the functionality of the MCP23016. the iares (interrupt activity resolution) bit controls the sampling frequency of the gp port pins. the higher the sampling frequency, the higher the device current requirements. if this bit is ? 0 ? (default), the maximum time to detect the activity on the port is 32 ms (max.), which results in lower standby current. if this bit is ? 1 ?, the maximum time to detect activity on the port is 200 sec. (max.) and results in higher standby current. register 1-11: iocon0 - i/0 expander control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? iares bit 7 bit 0 bit 1-7 unimplemented bit: read as ?0? bit 0 iares : interrupt activity resolution 1 = fast sample rate 0 = normal sample rate legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown iocon1 is a shadow register for iocon0. access to iocon1 results in access to iocon0.
MCP23016 ds20090c-page 12 ? 2007 microchip technology inc. 1.8 serializer/deserializer the serializer/deserializer block converts and transfers data between the i 2 c bus and gpio. 1.9 interrupt logic the MCP23016 asserts the open-drain interrupt output (int ) low when one of the port pins changes state. only those pins that are configured as an input can cause an interrupt. pins defined as an output have no effect on int. the interrupt will remain active until a read from either the port (gpn) on which the interrupt occurred or the intcapn register is performed. if the input returns to its previous state before a read operation, it will reset the interrupt and the int pin output will tri-state. each 8-bit port is read separately, so reading gp0 or intcap0 will not clear the interrupt generated by gp1 or intcap1, and vice versa. input change activity on each port will generate an interrupt and the value of the particular port will be captured and copied into intcap0/intcap1. the intcapn registers are only updated when an interrupt occurs on int . these values will stay unchanged until the user clears the interrupt by reading the port or the intcapn register. if the input port value changes back to normal before a user-read, the int output will be reset. however, the intcap0/intcap1 will still contain the value of the port at the interrupt change. if the port value changes again, it will re-activate the interrupt and the new value will be captured. the first interrupt on change event following an interrupt reset will result in a capture event. any fur- ther change event that occurs before the interrupt is reset will not result in a capture event. 1.9.1 interrupt event detection the iares bit controls the resolution for detecting an interrupt-on-change event. if this bit is ? 0 ? (default), the maximum time for detecting a change of event is high, which results in lower standby current. if this bit is ? 1 ?, it takes less time for scanning the activity on the port and results in higher standby current. figure 1-2: reading portx after interrupt event port value port x port x gpx int is captured and written to intcapn port value is captured and written to intcapn read gpx or intcapn
? 2007 microchip technology inc. ds20090c-page 13 MCP23016 1.9.2 writing the registers to write to a MCP23016 register, the master i 2 c device needs to follow the requirements, as illustrated in figure 1-3. first, the device is selected by sending the slave address and setting the r/w bit to logic ? 0 ?. the command byte is sent after the address and determines which register will be written. table 1-3 shows the relationship of the command byte and register. the MCP23016 has twelve 8-bit registers. they are configured to operate as six 16-bit register pairs, supporting the device?s 16-bit port. these pairs are formed based on their functions (e.g., gp0 and gp1 are grouped together). the i 2 c commands apply to one register pair to provide faster access. the first data byte following a command byte is written into the register pointed to by the command byte, while the second data is written into another register in the same pair. for example, if the first byte is sent to olat1 (command byte 03h ), the next data byte will be written into the sec- ond register of that pair, olat0. if the first byte is writ- ten to olat0 (command byte 02h ), the second byte will be written to olat1. there is no limitation on the number of data bytes in one write transmission. figure 1-4 shows the case of multiple byte writes in one write operation. in this case, the multiple writes are made to the same data pair. figure 1-3: write to configuration registers (case 1) note: the bus must remain free until after the ninth clock pulse for a minimum of 12 s (see table 2-5 and figure 2-4). 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p address command byte data 1 data 2 ack scl held low until data is processed
MCP23016 ds20090c-page 14 ? 2007 microchip technology inc. figure 1-4: write to configuration registers (case 2) figure 1-5: write to output ports 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack address command byte data 1 data 2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p data 1 data 2 scl held low until data is processed scl held low until data is processed 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack d0 d6 d5 d4 d3 d2 d1 d7 ack p address command byte data 1 data 2 data valid t gpv0 data valid t gpv1 sda scl data on gp0 data on gp1 scl held low until data is processed
? 2007 microchip technology inc. ds20090c-page 15 MCP23016 1.9.3 reading the registers to read a MCP23016 register, the master needs to follow the requirements shown in figure 1-6. first, the device is selected by sending the slave address and setting the r/w bit to logic ? 0 ?. the command byte is sent after the address and determines which register will be read. a restart condition is generated and the device address is sent again with the r/w bit set to logic ? 1 ?. the data register defined by the command byte will be sent first, followed by the other register in the register pair. the logic for register selection is the same as explained in write mode ( section 1.9.2, ?writing the registers? ). the falling edge of the ninth clock initiates the register read action. the scl clock will be held low while the data is read from the register and is transferred to the i 2 c bus control block by the serializer/deserializer block. the MCP23016 holds the clock low after the falling edge of the ninth clock pulse. the configuration registers (or port control registers) are read and the value is stored. finally, the clock is released to enable the next transmission. there is no limitation on the number of data bytes in one read transmission. figure 1-8 shows the case of multiple byte read in one read operation. in this case, the multiple writes are made to the same data pair. figure 1-6: read from configuration register note: the bus must remain free until after the ninth clock pulse for a minimum of 12 s (see table 2-5 and figure 2-4). 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/ w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address command byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/ w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p sda scl scl held low until data is processed scl held low until data is processed 0
MCP23016 ds20090c-page 16 ? 2007 microchip technology inc. figure 1-7: read from input ports (case 1) note: it is assumed that command byte is already set to ? 00 ?. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p read signal (internal) for gp0 read signal (internal) for gp1 t rdd0 t rdd1 t icd0 t isd t icd1 data in gp0 data in gp1 int sda scl scl held low until data is processed
? 2007 microchip technology inc. ds20090c-page 17 MCP23016 figure 1-8: read from input ports (case 2) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from gp0 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp1 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp0 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from gp1 p note: it is assumed that command byte is already set to 00. sda scl
MCP23016 ds20090c-page 18 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds20090c-page 19 MCP23016 2.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss ......................................................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +6.5v total power dissipation (note 1) ............................................................................................................................ 1 .0 w maximum current out of v ss pin .......................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... .. 250 ma input clamp current, i ik (v i < 0, or v i > v dd ) ....................................................................................................... 20 ma output clamp current, i ok (v o < 0, or v o > v dd ) ................................................................................................ 20 ma maximum output current sunk by any i/o pin..................................................................................... .................... 25 ma maximum output current sourced by any i/o pin .................................................................................. ................. 25 ma maximum current sunk by combined ports ...................................................................................................... 200 ma maximum current sourced by combined ports ..................................................................................... ........... 200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
MCP23016 ds20090c-page 20 ? 2007 microchip technology inc. 2.1 dc characteristics table 2-1: dc characteristics dc characteristics standard operating conditions (unless otherwise stated) operating temperature: -40c t a +85c for industrial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.0 ? 5.5 v d002 standby current i dd ? 0.4 ma iares = 1 d003 standby current i pd ? 25 a iares = 0 input low voltage i/o ports v il d004 ttl buffer vss ? 0.15 v dd v for entire v dd range d004a vss ? 0.8v 4.5v v dd 5.5v d005 schmitt trigger buffer vss ? 0.2 v dd v input high voltage i/o ports v ih ? d006 ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d006a 0.25 v dd + 0.8v ?v dd v for entire v dd range d007 schmitt trigger buffer 0.8 v dd ?v dd v for entire v dd range input leakage current d008 i/o ports i il ?? 1.0 a vss v pin v dd , pin at hi-impedance d009 clk ? ? 5.0 a vss v pin v dd output low voltage d010 i/o ports v ol ??0.6vi ol = 8.5 ma, v dd = 4.5v output high voltage d010 i/o ports v oh v dd -0.7 ? ? v i oh = 3.0 ma, v dd = 4.5v d011 v dd start voltage to ensure internal por signal v por ?vss? v d012 v dd rise rate to ensure internal por signal s vdd 0.05 - ? v/ms note 1 dc trip point v tpor 1.5 1.7 1.9 v dc slow ramp d012 v dd rise rate to ensure internal por signal with pwrt enabled s vdd 0.05 ? ? v/ms note 1 dc current draw i por ? 5.0 ? a at 5.0v (1 /volt typical) note 1: these parameters are characterized but not tested. 2: data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 3: standby current is measured with all i/o in hi-impedance state and tied to v dd and v ss . 4: for rc clk, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2 r ext (ma) with r ext in kohm. 5: negative current is defined as coming out of the pin.
? 2007 microchip technology inc. ds20090c-page 21 MCP23016 figure 2-1: response time table 2-2: response time figure 2-2: test point clock timing table 2-3: test point clock timing table 2-4: power-up timer requirements v dd 1 parameter no. symbol characteristic min typ? max units conditions 1 response time 100 ? ? ns minimum time where a v dd transition from 5.0v to 0.0v to 5.0v will cause a reset. all times less than 100 ns will be filtered. parameter no. symbol characteristic min typ ? max units conditions f tp tp pin frequency ? 1.0 ? mhz measured at tp pin, iares = ? 1 ?. 2 t tp tp pin clk period ? 1.0 ? s measured at tp pin, iares = ? 1 ?. ? data in "typ" column is at 5v, +25c unless otherwise stated. these parameters are for design guidance only and are not tested. t tp 2 parameter no. symbol characteristic min typ ? max units conditions 3t pwrt power-up timer period ? 72 ? ms ? data in "typ" column is at 5v, +25c unless otherwise stated. these parameters are for design guidance only and are not tested.
MCP23016 ds20090c-page 22 ? 2007 microchip technology inc. figure 2-3: i 2 c bus start/stop bits timing table 2-5: i 2 c bus start/stop bits requirements param no. symbol characteristic min ty p max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition (note 1) setup time 400 khz mode 600 ? ? 91 t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated (note 1) hold time 400 khz mode 600 ? ? 92 t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? 93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? note 1: these parameters are characterized but not tested. 91 92 93 scl sda start condition stop condition 90
? 2007 microchip technology inc. ds20090c-page 23 MCP23016 figure 2-4: i 2 c bus data timing 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out 111
MCP23016 ds20090c-page 24 ? 2007 microchip technology inc. table 2-5: i 2 c bus data requirements param no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s (note 1) 400 khz mode 0.6 ? s 101 t low clock low time 100 khz mode 4.7 ? s (note 1) 400 khz mode 1.3 ? s 102 t r sda and scl rise time 100 khz mode ? 1000 ns (note 1) 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns (note 1) 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition (note 1) 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated (note 1) 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns (note 1) 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 1) (note 3) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s (note 1) 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) (note 2) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmis- sion can start (note 1) 400 khz mode 1.3 ? s c b bus capacitive loading ? 400 pf 111 t wait clock wait time after ninth pulse 100 khz mode 12 s ? s time the bus must remain free after the ninth clock pulse before a new transmission can start. 400 khz mode 12 s ? s note 1: these parameters are characterized but not tested. 2: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
? 2007 microchip technology inc. ds20090c-page 25 MCP23016 table 2-7: gp0 and gp1 timing requirements param no. symbol characteristic min typ. max units conditions t gpv0 gp0 output data valid time ?40?stp = 1mhz t gpv1 gp1 output data valid time ?50?s t rdd0 gp0 data read delay time ?40?s t rdd1 gp1 data read delay time ?50?s t isd0 gp0 interrupt set delay time ? ? 200 s iares = 1, tp = 1 mhz ? ? 32 ms iares = 0, tp = 1 mhz t isd1 gp1 interrupt set delay time ? ? 200 s iares = 1, tp = 1 mhz ? ? 32 ms iares = 0, tp = 1 mhz t lcd0 gp0 interrupt clear delay time (for read) ?100? stp = 1mhz t lcd1 gp1 interrupt clear delay time (for read) ?100? s note 1: these parameters are characterized but not tested.
MCP23016 ds20090c-page 26 ? 2007 microchip technology inc. figure 2-5: gp0 and gp1 port timings note: it is assumed that command byte is already set to ?00?. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 a2 a1 a0 d0 s 0 r/w =0 ack d6 d5 d4 d3 d2 d1 d7 ack address data from lsb or msb of register 1 2 3 4 5 6 7 8 9 d0 d6 d5 d4 d3 d2 d1 d7 ack data from msb or lsb of register p read signal(internal) for gp0 read signal(internal) for gp1 t rdd0 t rdd1 t icd0 t isd t icd1 data in gp0 data in gp1 int sda scl scl held low until data is processed
? 2007 microchip technology inc. ds20090c-page 27 MCP23016 3.0 package information 3.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic yywwnnn example: xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example: xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 0717017 MCP23016-i/sp 0710017 MCP23016-i/so 28-lead ssop yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx example: 0720017 MCP23016 28-lead qfn example: xxxxxxxx xxxxxxxx yywwnnn MCP23016 -i/ml 0710017 -i/ss 3 e 3 e 3 e 3 e
MCP23016 ds20090c-page 28 ? 2007 microchip technology inc. 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3
? 2007 microchip technology inc. ds20090c-page 29 MCP23016 28-lead plastic small outline (so) ? wide, 7.50 mm body [soic] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a ? ? 2.65 molded package thickness a2 2.05 ? ? standoff a1 0.10 ? 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 ? 0.75 foot length l 0.40 ? 1.27 footprint l1 1.40 ref foot angle top 0 ? 8 lead thickness c 0.18 ? 0.33 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052 b
MCP23016 ds20090c-page 30 ? 2007 microchip technology inc. 28-lead plastic shrink small outline (ss) ? 5.30 mm body [ssop] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a ? ? 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 ? ? overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 9.90 10.20 10.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 ? 0.25 foot angle 0 4 8 lead width b 0.22 ? 0.38 l l1 c a2 a1 a e e1 d n 1 2 note 1 b e microchip technology drawing c04-073 b
? 2007 microchip technology inc. ds20090c-page 31 MCP23016 28-lead plastic quad flat, no lead package (ml) ? 6x6 mm body [qfn] w ith 0.55 mm contact length n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package is saw singulated. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.20 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.20 contact width b 0.23 0.30 0.35 contact length l 0.50 0.55 0.70 contact-to-exposed pad k 0.20 ? ? d exposed d2 e b k e2 e l n note 1 1 2 2 1 n a a1 a 3 top view bottom view pad microchip technology drawing c04-105 b
MCP23016 ds20090c-page 32 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds20090c-page 33 MCP23016 appendix a: revision history revision a (december 2002) original data sheet for MCP23016 device. revision b (september 2003) 1. addition of output low voltage section to table 2-1 in electrical characteristics. 2. addition of output high voltage section to table 2-1 in electrical characteristics. revision c (january 2007) this revision includes updates to the packaging diagrams.
MCP23016 ds20090c-page 34 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds20090c-page 35 MCP23016 product identification system to order or obtain information (e.g., on pricing or deliv ery) refer to the factory or the listed sales office. part no. x /xx package temperature range device device: dstemp: 16-bit i 2 c i/o expander temperature range: i= -40 c to +85 c package: sp = plastic dip (300 mil body), 28-lead so = plastic soic, wide (300 mil body), 28-lead ss = plastic soic, (209 mil, 5.30mm), 28-lead ml = plastic quad, flat no leads (qfn), 28-lead examples: a) dstemp-i/p: industrial temperature, pdip package. a) dstemp-i/so: industrial temperature, soic package. a) dstemp-i/ss: industrial temperature, soic package. a) dstemp-i/ml: industrial temperature, qfn package.
MCP23016 ds20090c-page 36 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds20090c-page 37 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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